As integrated circuits become increasingly larger and more integrated, wire delay becomes one of the dominant factors in determining an integrated circuit's maximum operating frequency. Wire delay has a snowball effect in retarding an integrated circuit's operating frequency. Not only is an integrated circuit's operating frequency reduced as it takes longer for signals to travel from point A to point B, but when signals are transmitted from point A to points B and C, the variable nature of wire delay can lead to skew between copies of signals received at points B and C. To insure that this sort of skew does not lead to improper circuit operation, additional delay, for the purpose of alleviating skew between copies of a signal, must be built into a circuit.
Unfortunately, wire delay is highly dependent on manufacturing process and environmental variations, and integrated circuits must therefore be designed to function under a "worst case" wiring scenario. As a result, there exists a need for methods and apparatus which mitigate and/or eliminate wire delay as one of the dominant factors in determining an integrated circuit's maximum operating frequency.
Prior to the availability of area connections between an integrated circuit and its package (e.g., C4 solder bump technology), the only feasible way to distribute timing critical signals (e.g., clocks) was via the metal layers of the integrated circuit's fabrication technology.
Unfortunately, there are numerous contributors to wire delay and skew "on-chip". One source of delay and skew is routing mismatch. Routing mismatch encompasses factors such as non-ideal route lengths, topological differences, coupling differences, and process and temperature variations. For example, variations in ILD (inter-layer dielectric) thickness are a significant contributor to signal skew. Another source of delay and skew is repeater mismatch. Repeater mismatch encompasses factors such as non-ideal repeater placement, FET (field-effect transistor) mismatch, across die variations in temperature, and local power supply differences. Differences in local signal loading are also a significant contributor to signal delay and skew.
Now that area connections between an integrated circuit and its package are available, attempts have been made to move timing critical signal distribution networks onto an integrated circuit's package. For example, Zhu and Dai propose a package clock distribution scheme in a paper entitled "Chip and Package Co-Design Technique for Clock Networks", which was presented at the 1996 IEEE Multi-Chip Module Conference (Feb. 6-7, 1996), and in a paper entitled "Planar Clock Routing for High Performance Chip and Package Co-Design", which was published in IEEE Transactions on Very Large Scale Integration (Vol. 4, No. 2, June 1996). Package clock distribution is further discussed by Zhu and Tam in a paper entitled "Package Clock Distribution Design Optimization for High-Speed and Low-Power VLSI's", which was published in IEEE Transactions on Components, Packaging, and Manufacturing Technology (Part B., Vol. 20, No. 1, February 1997). So that a complete background of package signal distribution need not be restated herein, these papers are hereby incorporated by reference for all that they disclose.
Theoretically, the distribution of timing critical signals via an integrated circuit package layer should mitigate the differences seen between copies of the signals received at remote corners of an integrated circuit, thus enabling a higher frequency of operation for the integrated circuit, and therefore, higher performance for a given integrated circuit fabrication technology. There are many factors which support this "theoretical" advantage. First, package wiring has less resistance than on-chip wiring. While package wiring is typically formed of copper, on-chip wiring is typically formed of an aluminum alloy. Furthermore, package wires can be made wider and thicker than on-chip wires (and thus, the resistance associated with package wiring may be further reduced).
An additional advantage of package wiring is that on-chip metal utilization is reduced. As a result, a smaller die size and/or fewer layers of metal may be used in an integrated circuit fabrication process, and signal delay and skew may be further reduced (if the die is smaller, signals do not have to travel as far). Alternatively, on-chip area which is freed by moving signal routes to the package can be used for added functionality (e.g., larger caches, additional functional units, etc.).
Yet another advantage of package wiring is that there are fewer sources of signal skew on-package. Similarly to on-chip signal routes, skew caused by routing mismatch still exists (e.g., non-ideal route lengths, ILD variations, etc.). However, many sources of routing skew are reduced. For example, skew induced by manufacturing process variation is far less, and skew attributable to repeater mismatch is eliminated (since repeaters are not used in conjunction with package wiring).
However, in spite of these "theoretical" advantages, many of them have yet to be realized, or have not been realized to their full extent. Most importantly, package signal distribution has yet to offer significantly faster signal distribution. Nor has package signal distribution resulted in a significantly better signal (e.g., a faster clock, with less skew, better edges, etc.).
It is therefore a first object of this invention to provide improved methods and apparatus for package signal distribution, wherein timing critical signals such as clocks may be distributed to distant locations of an integrated circuit with less delay and skew.
Another object of this invention is to provide methods and apparatus which free on-chip area for added functionality (and/or use of a smaller die).
Yet another object of this invention is to provide methods and apparatus which can be implemented utilizing existing manufacturing technologies and integrated circuit fabrication processes.